1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device.
2. Description of the Related Art
Semiconductor devices using a silicon carbide (SiC) semiconductor (hereinafter referred to as a silicon carbide semiconductor device) are recently attracting attention as devices that exceed the limitations of semiconductor devices using a silicon (Si) semiconductor material. In particular, silicon carbide semiconductor devices are expected to be applied to high voltage devices by taking advantage of characteristics of higher critical field strength and higher thermal conductivity as compared to silicon semiconductor materials. However, in producing (manufacturing) a practical silicon carbide semiconductor device, it is important to form an edge termination structure stably providing a high breakdown voltage. An edge termination structure portion is a region surrounding a periphery of an active region and relaxes electric field on the substrate front surface side of the active region to retain the breakdown voltage. The active region is a region through which current flows in an on-state.
The breakdown voltage of a device is usually limited by the electric field concentration on an outer peripheral portion of a p-type high-concentration region that is formed on a front surface side of an n−-type semiconductor substrate (semiconductor chip) serving as an n−-type drift layer and that extends from the active region to near an boundary between the active region and the edge termination structure portion. For example, in the case of a pn junction diode, this p-type high-concentration region is a p-type anode region forming a pn junction with the n−-type drift layer. Therefore, a junction termination extension (JTE) structure is known in which a p−-type low-concentration region having an impurity concentration that is lower than that of the p-type high-concentration region is formed adjacent to an outside (chip outer peripheral side) end portion of the p-type high-concentration region so as to relax the electric field on the edge termination structure portion.
In the JTE structure, a depletion layer extends from a pn junction between the p-type high-concentration region and the n−-type drift layer toward the outside and spreads to both the p-type high-concentration region and the p−-type low-concentration region. As a result, the electric field is relaxed on an outer peripheral portion of the p-type high-concentration region and therefore, the breakdown voltage may be improved. If this JTE structure is applied to an element having a higher breakdown voltage, the electric field concentrates also on an outer peripheral portion of the p−-type low-concentration region and the breakdown voltage is therefore limited by avalanche breakdown in the outer peripheral portion of the p−-type low-concentration region making up the JTE structure. Such problems may be prevented by gradually reducing the impurity concentration of the p−-type low-concentration region in the outward direction from an inner side (the active region side).
The JTE structure made up of the p−-type low-concentration region having an impurity concentration distribution gradually decreasing in the outward direction from the inner side in this way is referred to as a variation of lateral doping (VLD) structure. Since electric field concentration points are distributed to multiple locations in the VLD structure, the critical electric field intensity is significantly reduced. In the case of the silicon carbide semiconductor device having an extremely small thermal diffusion of impurities and subjected to ion implantation with high acceleration voltage for introducing impurities, it is difficult to apply the VLD structure to reduce the impurity concentration of the p−-type low-concentration region in the outward direction from the inner side. Therefore, the JTE structure must be configured by adjacently forming multiple p−-type low-concentration regions such that a region disposed on the outer side has a lower impurity concentration or a thinner thickness.
In the case of configuring the JTE structure made up of multiple p−-type low-concentration regions different in impurity concentration or thickness, it is preferable to increase the number of the p−-type low-concentration regions to make an impurity concentration difference of neighboring p−-type low-concentration regions as small as possible from the viewpoint of breakdown voltage performance of a device. However, this leads to an increase in the number of processes and is, therefore, a factor preventing a reduction in manufacturing cost. Currently, the silicon carbide semiconductor devices are typically provided with a JTE structure made up of multiple p−-type low-concentration regions having impurity concentration or thicknesses changed in two or three stages. A typical JTE structure of the silicon carbide semiconductor devices will be described by taking a Schottky barrier diode (SBD) as an example.
FIGS. 15A and 15B are explanatory views of a conventional SiC-SBD structure. FIG. 15A depicts a planar layout and FIG. 15B depicts a cross-sectional structure taken along a cutting line AA-AA′ of FIG. 15A. As shown in FIGS. 15A and 15B, for example, at a breakdown voltage of 600 V or 1200 V, an edge termination structure portion 112 surrounding a periphery of an active region 111 is typically provided with a JTE structure made up of two p-type regions (a p−-type region 104 and a p−−-type region 105) different in impurity concentration. For example, a silicon carbide epitaxial layer serving as an n−-type drift layer 102 is deposited on a front surface of an n+-type silicon carbide substrate 101. An epitaxial substrate made up of the n+-type silicon carbide substrate 101 and the n−-type drift layer 102 will hereinafter be referred to as a silicon carbide base (semiconductor chip).
A surface layer of the front surface (a surface on the n−-type drift layer 102 side) of the silicon carbide base has a p-type guard ring 103 selectively disposed at a boundary between the active region 111 and the edge termination structure portion 112 from the active region 111 into the edge termination structure portion 112. The p-type guard ring 103 surrounds a periphery of a Schottky junction between the n−-type drift layer 102 and an anode electrode 108 in the active region 111. In the edge termination structure portion 112, the surface layer of the front surface of the silicon carbide base has a JTE structure disposed outside the p-type guard ring 103 to surround a periphery of the p-type guard ring 103. The JTE structure is made up of the p−-type region 104 and the p−−-type region 105 (hereinafter referred to as the first JTE region 104 and the second JTE region 105).
The first JTE region 104 surrounds the periphery of the p-type guard ring 103 and contacts an outside end portion of the p-type guard ring 103. The impurity concentration of the first JTE region 104 is lower than the impurity concentration of the p-type guard ring 103. The second JTE region 105 is disposed outside the first JTE region 104 to surround a periphery of the first JTE region 104 and contacts an outside end portion of the first JTE region 104. The impurity concentration of the second JTE region 105 is lower than the impurity concentration of the first JTE region 104. Both the first and second JTE regions 104, 105 have a uniform impurity concentration distribution. Reference numerals 107, 109 denote an interlayer insulating film and a cathode electrode.
As a result of intensive studies by the inventors, the breakdown voltage may be ensured up to the 1200 V by the JTE structure depicted in FIGS. 15A and 15B; however, it has been confirmed that the electric field concentration becomes significant at a higher breakdown voltage class on the boundary between the first JTE region 104 and the second JTE region 105. The occurrence of the electric field concentration on the boundary between the first JTE region 104 and the second JTE region 105 causes a problem of reduction in manufacturing process margins necessary for ensuring a predetermined breakdown voltage of the edge termination structure portion 112. The manufacturing process margins necessary for ensuring a predetermined breakdown voltage of the edge termination structure portion are margins of the breakdown voltage of the edge termination structure portion for ion implantation accuracy (a dose amount, a diffusion depth) and an electrical activation rate when a p-type region making up the JTE structure is formed.
The problem related to such manufacturing process margins may be improved by increasing the number of p-type regions making up the JTE structure and by arranging multiple p-type regions such that the p-type regions with a small impurity concentration difference are adjacent to each other, so as to reduce the impurity concentration in stages from the inner side toward the outside. However, the number of processes of photolithography and ion implantation is increased by the increased number of p-type regions making up the JTE structure, leading to a new problem of cost increase. Thus, concerning the JTE structure of silicon carbide semiconductor devices various proposals have been made for relaxing the electric field of the JTE structure.
In a proposed device in which the electric field of the JTE structure is relaxed, multiple p-type subregions having the same impurity concentration as a first JTE region are disposed in a ring shape surrounding the first JTE region in a portion of a second JTE region close to the first JTE region (see, e.g., Japanese Laid-Open Patent Publication No. 2008-034646 (paragraph 0033, FIG. 11)). In another proposed device with the electric field of the JTE structure relaxed, the JTE structure of Japanese Laid-Open Patent Publication No. 2008-034646 is further optimized (see, e.g., International Publication No. 2012/049872). In International Publication No. 2012/049872, a third JTE region surrounding a periphery of the second JTE region is further included, and multiple p-type subregions having the same impurity concentration as the second JTE region are disposed in a portion of the third JTE region close to the second JTE region.
FIGS. 16A and 16B depict a structure obtained by adding the JTE structures of Japanese Laid-Open Patent Publication No. 2008-034646 and International Publication No. 2012/049872 to the JTE structure having the two-layer structure of the first and second JTE regions 104, 105 in FIGS. 15A and 15B. FIGS. 16A and 16B are explanatory views of another example of the conventional SiC-SBD structure. In the JTE structure depicted in FIGS. 16A and 16B, an electric field relaxation region 120 made up of p−-type subregions 121 and p−−-type subregions 122 is disposed between the first JTE region 104 and the second JTE region 105. The p−−-type subregions 122 and p−-type subregions 121 are alternately repeatedly arranged in the outward direction from the inner side (the active region 111 side) to surround peripheries of p-type subregions adjacent on the inner side.
The impurity concentration of the p−-type subregions 121 is equal to the impurity concentration of the first JTE region 104. The width x11 of each of the p−-type subregions 121 (the width in the outward direction from the inner side, hereinafter simply, width) is less than the width of the first JTE region 104, and the farther the p−-type subregions 121 are disposed toward the outside, the a smaller width thereof is. The impurity concentration of the p−−-type subregions 122 is equal to the impurity concentration of the second JTE region 105. The width x12 of each of the p−−-type subregions 122 is less than the width of the second JTE region 105, and the farther the p−−-type subregions 122 is disposed toward the outside, the greater the width thereof is. In this manner, progressive variation of the respective widths x11, x12 of the p−-type subregions 121 and the p−−-type subregions 122 toward the outside gradually reduces the impurity concentration in the direction from the first JTE region 104 to the second JTE region 105 in this configuration.
In Japanese Laid-Open Patent Publication No. 2008-034646 and International Publication No. 2012/049872, the JTE regions are formed in a concentric shape surrounding the periphery of the active region, and the impurity concentration of the JTE regions is controlled by the dose amount of ion implantation. Further, in addition to a method of controlling the impurity concentration of the JTE region in this manner, a method of controlling the impurity concentration of respective JTE regions by changing the planar pattern of each JTE region has been reported. For example, a device including a second JTE region in which a p−-type region having the same impurity concentration and the same depth as a first JTE region is disposed in a mesh shape (a lattice shape) with the n−-type drift layer left in a matrix shape has been proposed (see, e.g., Japanese Laid-Open Patent Publication No. 2011-187767). A JTE structure in Japanese Laid-Open Patent Publication No. 2011-187767 is depicted in FIGS. 17A, 17B, and 18.
FIGS. 17A and 17B are diagrams of another example of a conventional SiC-SBD structure. FIG. 17A depicts a planar layout and FIG. 17B depicts a cross-sectional structure taken along a cutting line BB-BB′ of FIG. 17A. FIG. 18 is an enlarged plan view of a principal part depicted in FIG. 17A. FIG. 18 depicts an enlarged view of a portion surrounded by a rectangular frame 130 of FIG. 17A. As depicted in FIGS. 17A, 17B, and 18, in Japanese Laid-Open Patent Publication No. 2011-187767, the n−-type drift layer 102 is selectively left within a second JTE region 132 having the same impurity concentration and the same depth as a first JTE region 131, which is equivalent to disposing a JTE region having an impurity concentration lower than the first JTE region 131 on the outside of the first JTE region 131.
Japanese Laid-Open Patent Publication No. 2011-187767 describes that the n−-type drift layer 102 left in a matrix shape may be changed in width and arrangement density to change the proportion of the n−-type drift layer 102 occupying the inside of the second JTE region 132 so as to produce a predetermined impurity concentration distribution. The JTE structures described in Japanese Laid-Open Patent Publication No. 2008-034646, International Publication No. 2012/049872, and Japanese Laid-Open Patent Publication No. 2011-187767 are known as improvement items not only for the JTE structure of the silicon carbide semiconductor device but also for the VLD structure described above. For example, a method of obtaining a predetermined impurity concentration distribution of the JTE region by forming a p−-type region in a predetermined planar pattern by ion implantation using, as a mask, an oxide film having openings in a mesh or matrix shape pattern has been proposed (see, e.g., Japanese Laid-Open Patent Publication No. 2014-038937 (paragraph 0050, FIG. 3)). Further, a method of forming an ion implantation mask by unit masks having a circular shape, a rectangular shape, or a plus “+” has been proposed (see, e.g., Japanese Laid-Open Patent Publication No. 2011-165856). In Japanese Laid-Open Patent Publication No. 2011-165856, in the respective formation regions of JTE regions, the ion implantation masks are formed so that the dimensions and arrangement intervals of the unit masks differ from each other.
As another method of forming a JTE structure, the following method has been proposed in terms of formation of a JTE structure made up of a first JTE region, a second JTE region disposed outside the first JTE region and having an impurity concentration lower than the first JTE region, and a third JTE region that is made up of first and second p-type subregions different in impurity concentration disposed between the first JTE region and the second JTE region and that has an average impurity concentration between the first JTE region and the second JTE region. Ion implantation is performed by using a first mask to form the same impurity layer as the second JTE region such that the impurity layer reaches a formation region of the first JTE region and to form the second subregions. Thereafter, ion implantation is performed by using a second mask at least covering the second JTE region to form the first JTE region and the first subregions (see, e.g., International Publication No. 2012/049872).